Open to SI / PI & Advanced Packaging Roles

Kruthik Reddy
Purumandla.

Signal Integrity, Power Integrity, and Advanced Semiconductor Packaging engineer. I model high-speed channels, PDNs, and 2.5D packages from full-wave EM extraction to post-layout correlation.

M.S. EE, Arizona State University HFSS 3D Layout · SIwave · ADS Tempe, AZ
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CH1 · HBM3 Channel · 6.4 Gbps NRZ EYE / LIVE
Insertion Loss-2.4 dB
NEXT / FEXT< -39 dB
Nyquist3.2 GHz
16-port
HBM3 S-Parameter Network
2 mΩ
Min PDN Impedance · 4.5x Margin
26%
Peak Temp Reduction · 2.5D vs 2D
<0.7 dB
Phase Shifter Insertion Loss
Core Systems

Engineering Domains

Three tightly coupled disciplines, one workflow: extract, analyze, correlate, and co-design across die, package, and board.

Signal & Power Integrity

S-parameter extraction, crosstalk quantification, and PDN impedance modeling for high-speed chiplet systems. Full-wave EM of via transitions, routing, and decoupling strategies.

S-ParametersNEXT / FEXTPDN ImpedanceSI/PI Co-Sim

Advanced Packaging

2D/2.5D chiplet models with silicon interposers, micro-bump arrays, TSVs, and RDL stackups. Warpage, CTE-driven strain, and thermo-mechanical reliability feeding SI/PI-aware co-design.

2.5D InterposerMicrobump / TSVWarpage & CTEThermal Stress

RF & Analog IC

Schematic through EM co-simulation: reflective phase shifters, power dividers, multi-class PAs, and folded-cascode CMOS amplifiers across DC, AC, and transient corners.

Keysight ADSMomentum EMCadence VirtuosoRF PAs
Projects

Featured Engineering Work

Simulation-driven programs spanning package-level SI/PI, PDN design, RF co-simulation, and full-custom analog. Expand each for the technical record.

01 · SI/PI · Advanced Packaging

HBM3 Channel SI/PI Co-Simulation on a 2.5D Silicon Interposer

Full-wave modeling of a 4-pair HBM3 differential channel on a 2.5D silicon interposer, from 16-port extraction in HFSS 3D Layout through coupled-plane PDN design in SIwave.

Insertion Loss-2.4 dB
NEXT / FEXT< -39 dB
Data Rate6.4 Gbps NRZ
PDN Margin4.5x
ANSYS HFSS 3D LayoutANSYS SIwave
Technical Record
  • Modeled a 4-pair HBM3 differential channel on a 2.5D silicon interposer in HFSS 3D Layout; extracted 16-port S-parameters yielding -2.4 dB insertion loss and < -39 dB NEXT/FEXT at the 3.2 GHz Nyquist for 6.4 Gbps NRZ
  • Ran a 4-point parametric crosstalk study (8 to 15 µm spacing), quantifying ~1 dB/µm NEXT/FEXT improvement with IL/RL held constant, cleanly isolating the coupling variable to derive the routing-density vs. SI trade-off
  • Built a coupled-plane PDN in SIwave (1 MHz to 2 GHz); achieved 2 mΩ minimum impedance at the 95 MHz decap SRF against a 9.2 mΩ target (4.5x margin); decap-count sensitivity sweep showed 3x degradation with 50% of decaps removed
02 · Thermo-Mechanical · Packaging

2D/2.5D Chiplet Package Thermal-Structural Modeling

Comparative package study in ANSYS Mechanical linking thermal gradients, CTE mismatch, and warpage to signal and power integrity risk in high-density interconnects.

Peak Temp Reduction26%
Thermal Sweep75 to 125°C
Die Power2.5 W + 1 W
ANSYS Mechanical
Technical Record
  • Modeled 2D and 2.5D chiplet packages with logic (2.5 W) and memory (1 W) dies, silicon interposer, microbumps, and underfill, simulating thermal-structural response across 75 to 125°C to achieve a 26% peak temperature reduction in the 2.5D configuration
  • Localized von Mises stress hotspots at die corners driven by CTE mismatch and out-of-plane warpage, linking thermal gradients to degraded signal integrity and PDN performance in high-density interconnects
03 · RF · EM Co-Simulation

Reflective-Type PIN Diode Phase Shifter, 2.7 to 3.0 GHz

Two-state reflective phase shifter built on a branch-line hybrid with DSG9500 PIN diode loads in Keysight ADS, correlated from schematic through Momentum EM co-simulation.

Return Loss< -15 dB
Insertion Loss< 0.7 dB
Phase Difference~86° to 96°
Keysight ADSMomentum EM
Technical Record
  • Designed a 2.7 to 3.0 GHz reflective phase shifter with a branch-line hybrid and DSG9500 PIN diodes (forward/reverse bias states) on a 20 mil substrate (εr = 3.55) in Keysight ADS; achieved < -15 dB return loss, < 0.7 dB insertion loss, and ~86° phase difference between states
  • Integrated vendor component models (Murata capacitors, Coilcraft RF choke, Panasonic bias resistor) into the 5 V DC bias network for state switching
  • Correlated Momentum EM co-simulation against schematic, observing a ~7 to 10° phase increase (to ~93 to 96°) from layout parasitics and EM coupling
04 · Analog IC Design

High-Performance Folded-Cascode CMOS Amplifier

Full-custom folded-cascode amplifier with beta-multiplier biasing in Cadence Virtuoso, validated across DC, AC, and transient corners under load and bias variation.

Bias Current666 µA
Power2 mW
Output Swing1.06 V
Cadence VirtuosoADE-L
Technical Record
  • Designed a folded-cascode CMOS amplifier with beta-multiplier biasing in Cadence Virtuoso, sizing transistors for gain, bandwidth, phase margin, and stability targets
  • Validated via DC/AC/transient analysis achieving 666 µA bias current, 2 mW power, and 1.06 V output swing from a 3 V supply
05 · RF · Microwave

Wilkinson Power Divider on Rogers RO4003C

Microstrip Wilkinson divider for the 5.65 to 5.925 GHz band, validated for return loss, power split balance, and port isolation via S-parameter analysis and Momentum EM co-simulation.

Band5.65 to 5.925 GHz
SubstrateRO4003C
Keysight ADSMomentum EM
Technical Record
  • Designed a 5.65 to 5.925 GHz Wilkinson divider on Rogers RO4003C using microstrip transmission lines
  • Validated return loss, equal power split, and port isolation through circuit-level S-parameter analysis and Momentum EM co-simulation agreement
06 · Computational Modeling

Cleanroom Airflow & Particle-Transport Simulation

Python simulation of 0.5 µm particle distribution in a 10x10x1 ft³ cleanroom slice, modeling recirculation zones, HEPA/ULPA filtration, and equipment blockages to classify cleanliness.

Benchmark Match2.1848 /min
Best CaseISO Class 4
PythonNumPyMatplotlib
Technical Record
  • Built a grid-based airflow model with columnar, diverging, and merging particle transport logic across recirculation zones
  • Validated against the provided test case, matching the 2.1848 particles/min filter-penetration benchmark
  • Simulated four scenarios including improved filtration (ISO Class 4), air handler failure (Class 1000), and a realistic case using published industry parameters
  • Determined ISO 14644 and Fed. Std. 209E classifications from per-cell particle count outputs
Trajectory

Experience

Teaching, hardware development, and fabrication experience connecting design simulation to physical realization.

Jan 2025 to Present

Graduate Service Assistant

Arizona State University · Tempe, AZ
  • Guided students on cleanroom design and layout constraints in the Semiconductor Fabrication Cleanroom course
  • Assisted with MATLAB-Arduino labs for the Systems Dynamics and Controls course, supporting experiments and grading
Nov 2023 to Apr 2024

Electronics Engineer Intern

Wisda Energy · Hyderabad, India
  • Designed a low-noise analog front-end for solar sensing signals, reducing noise susceptibility by 22% during system validation
  • Validated analog signal paths using LTSpice to ensure stable gain behavior prior to PCB implementation
  • Integrated sensor conditioning and ADC scaling into the control module, improving measurement reliability
Jun 2023 to Sep 2023

Electronics Design Engineer Intern

iTIC Incubator, IIT Hyderabad · Hyderabad, India
  • Conditioned piezoelectric sensor signals using analog amplification and filtering to reduce noise before ADC digitization
  • Modeled the analog signal chain in LTSpice to validate gain and noise performance prior to hardware testing
  • Debugged signal noise using an oscilloscope and interfaced digitized sensor data with an Arduino-based IoT module
Instrumentation

Engineering Stack

Tooling across EM simulation, package co-design, analog IC, lab measurement, and analysis, organized as functional modules.

Signal & Power Integrity

Signal IntegrityPower IntegrityPDN AnalysisInterconnect ParasiticsHigh-Speed Interconnects

Semiconductor Packaging

2D / 2.5D Chiplet PackagingThermo-Mechanical ReliabilityThermal Analysis

EDA & Simulation

ANSYS HFSS / 3D LayoutANSYS SIwaveANSYS Q2DANSYS MechanicalKeysight ADSCadence VirtuosoLTSpiceKiCad

Measurement & Validation

VNATDROscilloscopeSpectrum AnalyzerPCB DebuggingHardware Signal Validation

Programming & Analysis

PythonMATLABCC++NumPyMatplotlibMS Excel

Domains

HBM ChannelsS-Parameter ExtractionCrosstalk / NEXT / FEXTRF Circuit DesignAnalog Front-Ends
Foundation

Education & Certifications

Graduate training in ASU's advanced packaging and analog IC programs on a strong EE foundation.

May 2026

M.S. Electrical Engineering · GPA 3.73 / 4.0

Arizona State University · Tempe, AZ
Key Coursework
Co-Design for Advanced Semiconductor Packaging · Advanced Analog ICs · Analog-to-Digital Converters · RF Transmitters · Microwave Circuit Design · Computer Architecture · CMOS & MEMS · Semiconductor Fabrication & Cleanroom Practices
August 2024

B.Tech. Electrical & Electronics Engineering

Mahindra University · Hyderabad, India
Key Coursework
Analog IC Design · VLSI Design · Semiconductor Devices · Digital Electronics
Certifications
HFSS 3D Layout - Getting Started · Ansys · Mar 2026 Ansys HFSS Introduction · Mar 2026 Transmission Lines 101 · Dr. Eric Bogatin · The EEcosystem Masterclass
Link Established

Let's build the next
high-speed system.

Open to Signal / Power Integrity, advanced semiconductor packaging, and analog IC design opportunities.

kruthikpurumandla79@gmail.com (602) 807-8788 LinkedIn